This invention relates to a nonvolatile semiconductor memory device.
EPROMs including floating gate MOS FETs as memory cells are generally used as nonvolatile semiconductor memories. Data are written into the EPROM through the effect of injection of the electrons into the floating gate. These electrons which are separated from holes by impact ionization in a pinch-off region formed in the vicinity of the drain when a high voltage is applied to the drain and control gate of a floating gate MOS FET. FIG. 1 shows an example of a prior art EPROM. The output signal of a memory array 2 formed of floating gate MOS FETs 1 is supplied to an input terminal of a differential sense amplifier 4, while the output signal of a reference signal generator 6, including floating gate MOS FETs 5 with the same configuration of the MOS FETs 1 forming the memory array 2, is supplied to the other input terminal of the differential sense amplifier 4. A gate signal generator 8 is connected to the control gate of the MOS FETs 5 in the reference signal generator 6. The output signal of the differential sense amplifier 4 is read out by means of an output buffer (not shown), and used as data.
At the time of reading, a specified memory cell in the memory array 2 is selected. The state of conduction of the memory cell depends on whether or not the floating gate is injected with electrons. Thus, the output line of the memory array 2 is charged or discharged. The output level of the sense amplifier 4 depends on the difference between the level of the output line of the memory array 2 and the output level of the reference signal generator 6. If the output voltages of the memory array 2 and the reference signal generator 6 are VA and VB, respectively, the output level of the sense amplifier 4 is logic 1 level where VA.degree.VB, and logic 0 level where VA&lt;VB. If the gate voltage of the transistor 5 in the reference signal generator 6, i.e. the output voltage of the gate signal generator 8, is VR, VB is equal to VA corresponding to the gate voltage of the selected memory cell at VR when the memory cell is neutral, that is, when the floating gate is not injected with electrons.
If VR=0.6 VC is given by resistors between VC and VS in the gate signal generator 8, the gate potential of the selected memory cell is substantially equal to VC. If a neutral cell is selected, the relationship of VA&lt;VB is established, so that the output level of the sense amplifier 4 becomes logic 0. If a written cell is selected, on the other hand, the relationship of VA&gt;VB is established, so that the output level of the sense amplifier 4 becomes logic 1.
In order to check up the amount of data written in the memory cell, there will be investigated the minimum value of the threshold voltage of the memory cell whereby it is given as a conclusion that data is written in the memory cell. Since the MOS FET 5 for generating the reference signal is equivalent to the MOS FET 1 of the memory cell, a current flowing through both these MOS FETs is in proportion to the difference between the gate voltage and the threshold voltage. VA.degree.VB may be obtained under the following condition: EQU VC-VTH&lt;VR-VTH' (1)
Here VTH and VTH' are the threshold voltages of the MOS FETs 1 and 5, respectively.
Substituting VR=0.6 VC into Expression (1), we obtain the following condition: EQU VTH.degree.0.4 VC+VTH' (2)
If VC=5.5 V and VTH'=1.5 V are given, the threshold voltage VTH of the memory cell is more than 3.7 V. Namely, data may be written in the memory cell at a voltage higher than 3.7 V as compared with the supply voltage of 5.5 V even if the MOS FET in the memory cell is not perfectly cutoff due to the electrons injected into the floating gate.
It is important, to check the memory cells of the EPROM for acceptablity, e.g. data holding capability before shipment. In a general test on an EPROM, the product is exposed to a high temperature after data is written, and then the threshold voltage VTH of the memory cell is detected. For this purpose, the supply voltage VC, i.e. the gate voltage of the memory cell, is changed, and a supply voltage VC' for the inversion of the state of the memory cell is detected. Suppose when the supply voltage VC' of the memory cell is 7 V, the memory data is inverted. The memory data is inverted when the supply voltage VC' is 6 V after high heating testing. Then, it may be given as a conclusion of high heating test that the electrons have slipped out of the floating gate, revealing defective insulation of the floating gate. Subsequently, as regards the EPROM of FIG. 1, the minimum value of the supply voltage VC to invert the output data is sought for. If the threshold voltage VTH of the memory cell is 5.5 V, VC is obtained by reversing the sign of inequality of Expression (2) as follows: EQU 5.5&lt;0.4 VC+1.5 EQU VC.degree.10.0
Namely, the data is inverted when the supply voltage is higher than 10 V. The higher the threshold voltage VTH of the memory cell in which the data is written necessitates the higher the supply voltage. However, it is not advisable to apply such a high voltage to the memory because transistors in a circuit with 5 V power supply may possibly be broken. Thus, the EPROM of this type cannot be checked before shipment, leaving room for improvement in reliability.
Operations of a MOS FET may be classified by biasing conditions into two modes; saturated operation (pentode operation) and unsaturated operation (triode operation). These two modes of operation may be expressed, respectively, as follows: EQU VG-VTH-VS.ltoreq.VD-VS (3) EQU VG-VTH-VS&gt;VD-VS (4)
VG is the control gate voltage; VD, drain voltage;
VS, source voltage; and VTH, threshold voltage.
It is known that the pentode operation of the MOS FET would produce a pinch-off region. In the EPROM of FIG. 1, the gate voltage of the MOS FET 5 in the reference signal generator 6 is lower than VC, so that the operation of the MOS FET 5 resembles the pentode operation more than the operation of the memory cell does. Accordingly, electrons may possibly be accumulated gradually in the floating gate of the floating gate MOS FET 5 during prolonged use. As a result, the reference voltage of the differential sense amplifier 4 may be varied to change the speed of data reading from the memory array 2 or to cause wrong data decision. Thus, the reliability of the memory is lowered.
In other conventional ROMs than the EPROM, moreover, the data readout time depends on the charge and discharge time of the output line. As the memory capacity increases, therefore, the stray capacity of the output line increases to prolong the readout time.